A Fully Automated SPICE-Compatible Netlist Extraction From Image Using Deep Learning and Image Preprocessing Techniques

This paper presents an automated framework for generating SPICE compatible netlists from both printed and hand-drawn circuit diagrams. The system combines advanced image preprocessing, deep learning based object detection, and contour based node analysis to address challenges such as inconsistent drawing styles, illumination variations, and non-standardized symbols. A unified preprocessing module incorporating denoising, contrast enhancement, adaptive thresholding, morphological filtering, and skeletonization ensures robust inputs for downstream tasks. Multiple YOLO (You Only Look Once) architectures were trained and evaluated, demonstrating strong performance across subtasks: YOLOv8L achieved 97.50% for transistor detection, YOLOv11L reached 98.55% for terminal segmentation, YOLOv11X attained 96.13% for voltage segmentation, and YOLOv8L obtained 99.23% for ground detection. These results confirm the framework's reliability in symbol interpretation. Beyond component-level recognition, the system integrates a specialized transistor terminal segmentation model and an advanced contour-based node detection module, enabling the accurate extraction of connectivity, even in dense, multi-component circuits. A novel validation mechanism further enhances robustness by fully automated simulating generated netlists in LTSpice and comparing node voltages with those of reference designs. Experimental evaluation demonstrates superior performance on printed diagrams (93.33% accuracy) and competitive performance on hand-drawn sketches (85.33% accuracy), despite stylistic irregularities. Overall, the proposed pipeline provides a scalable and accurate end-to-end solution, reducing human error and ensuring functional equivalence. Its ability to process complex, large-scale hand-drawn schematics under diverse conditions highlights its contributions to Electronic Design Automation (EDA), industrial applications, and intelligent design assistance. In addition, the framework incorporates a fast and fully automated validation stage, where generated netlists are systematically simulated in LTspice and compared against reference designs. This ensures both structural correctness and functional equivalence, further enhancing robustness and reliability.