NeuralTimer: Configuration-Based Neural Network Approach to Hardware Timer-Based Applications

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dc.authorid0009-0006-2362-6219
dc.contributor.authorAkmandor, Melike Ozlem
dc.contributor.authorSarioglu, Baykal
dc.date.accessioned2026-04-04T18:55:50Z
dc.date.available2026-04-04T18:55:50Z
dc.date.issued2026
dc.departmentİstanbul Bilgi Üniversitesi
dc.description.abstractHardware timers are fundamental components in time-critical embedded systems, where precise and deterministic timing control is essential for operations such as real-time signal processing, task scheduling, sensor data acquisition, and synchronization. Even small timing inaccuracies can lead to degraded performance or system malfunction. This paper presents a novel NeuralTimer architecture that replaces conventional register-based timer logic with a compact neural network implemented on the Xilinx Zybo Z7-20 FPGA platform. The design operates at the board's native 125 MHz clock frequency and realizes an 8-bit threshold-based timing mechanism capable of adaptive and high-level timing control. Unlike traditional timers that require hardware-dependent configuration through prescalers and registers, the proposed approach enables reconfiguration simply by updating the neural network weights. Experimental validation demonstrates stable real-time performance confirming that neural-network-driven timers can serve as flexible, resource-efficient, and reconfigurable control primitives for next-generation embedded systems.
dc.identifier.doi10.1109/ACCESS.2026.3656830
dc.identifier.doi10.1109/ACCESS.2026.3656830
dc.identifier.endpage13563
dc.identifier.issn2169-3536
dc.identifier.scopus2-s2.0-105028402417
dc.identifier.scopusqualityQ1
dc.identifier.startpage13544
dc.identifier.urihttps://doi.org/10.1109/ACCESS.2026.3656830
dc.identifier.urihttps://hdl.handle.net/11411/10579
dc.identifier.volume14
dc.identifier.wosWOS:001674724600019
dc.identifier.wosqualityQ2
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIeee-Inst Electrical Electronics Engineers Inc
dc.relation.ispartofIeee Access
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/openAccess
dc.snmzKA_WoS_20260402
dc.snmzKA_Scopus_20260402
dc.subjectHardware
dc.subjectField Programmable Gate Arrays
dc.subjectTiming
dc.subjectLogic
dc.subjectHardware Design Languages
dc.subjectRegisters
dc.subjectTraining
dc.subjectReal-Time Systems
dc.subjectEmbedded Systems
dc.subjectNeurons
dc.subjectField-Programmable Gate Array (Fpga)
dc.subjectHardware Timer
dc.subjectNeural Network
dc.titleNeuralTimer: Configuration-Based Neural Network Approach to Hardware Timer-Based Applications
dc.typeArticle

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