A 2.55-mW on-chip passive balun-LNA in 180-nm CMOS

Abstract

In this paper, an on-chip planar balun and a common-gate (CG) low-noise amplifier (LNA) employing a multiple feedback structure is presented. The planar interleaved balun is characterized through electromagnetic (EM) simulations using Advanced Design System (ADS) Momentum. A new lumped circuit model of the balun is created for use in transient simulations. CG-LNA employs g(m)-boosting and positive feedback structures to reduce the high noise figure (NF) of the traditional CG-LNA. The combined blocks achieve a minimum NF of 5.5 dB and an AC gain of 18.54 dB in post-layout simulations. The balun and LNA blocks are designed in a 180 nm CMOS technology using 1Poly6Metal (1P6M) layers. Simulation results are presented for post-layout and schematic cases. The total power consumption of the the circuit is 2.55 mW with 1.8 V nominal power supply. Furthermore, a time-domain UWB pulse simulation is done to confirm the operation of the blocks combined. These can be used to form the initial stages of an UWB receiver.