Akmandor, Melike OzlemSarioglu, Baykal2026-04-042026-04-0420262169-3536https://doi.org/10.1109/ACCESS.2026.3656830https://hdl.handle.net/11411/10579Hardware timers are fundamental components in time-critical embedded systems, where precise and deterministic timing control is essential for operations such as real-time signal processing, task scheduling, sensor data acquisition, and synchronization. Even small timing inaccuracies can lead to degraded performance or system malfunction. This paper presents a novel NeuralTimer architecture that replaces conventional register-based timer logic with a compact neural network implemented on the Xilinx Zybo Z7-20 FPGA platform. The design operates at the board's native 125 MHz clock frequency and realizes an 8-bit threshold-based timing mechanism capable of adaptive and high-level timing control. Unlike traditional timers that require hardware-dependent configuration through prescalers and registers, the proposed approach enables reconfiguration simply by updating the neural network weights. Experimental validation demonstrates stable real-time performance confirming that neural-network-driven timers can serve as flexible, resource-efficient, and reconfigurable control primitives for next-generation embedded systems.eninfo:eu-repo/semantics/openAccessHardwareField Programmable Gate ArraysTimingLogicHardware Design LanguagesRegistersTrainingReal-Time SystemsEmbedded SystemsNeuronsField-Programmable Gate Array (Fpga)Hardware TimerNeural NetworkArticle2-s2.0-10502840241710.1109/ACCESS.2026.365683010.1109/ACCESS.2026.365683013563Q11354414Q2WOS:001674724600019