Ramazanoglu, SemihBatur, Okan Zafer2024-07-182024-07-182018978-1-5386-4881-00271-4302https://doi.org/10.1109/ISCAS.2018.8351457https://hdl.handle.net/11411/7778IEEE International Symposium on Circuits and Systems (ISCAS) -- MAY 27-30, 2018 -- Florence, ITALYIn this paper, we present a new configurable switched capacitor loading technique to achieve a shunt capacitor variable delay line with reduced capacitor area. Proposed delay line employs only two configurable and switchable capacitors to achieve the required delay value. Thermometer coded capacitors are utilized for linear and nondecreasing delay. The proposed architecture has high linearity figures with 0,0104 DNL & 0,0618 INL. The delay steps can be configured with 100 pS/step. Maximum delay range of the 10 cascaded delay cells is 10 nS. The delay cells can be activated separately to increase the control over the required delay range. The maximum operating frequency of a single delay cell is 90 MHz. The delay line architecture is designed in UMC 180 nm CMOS technology and simulation results are presented. The circuit operates with 1.8 V supply and the core delay cell consumes 95 mu W at 10 MHz PRF. The delay line with 10 cascaded delay cells consumes 536 mu W at 5 MHz PRF. Achieved linearity value of R-2 is 0,9999.eninfo:eu-repo/semantics/closedAccessPhase-Locked LoopConference Object2-s2.0-8505708516810.1109/ISCAS.2018.8351457N/AN/AWOS:000451218702140